Transforming Dependence Graphs into Signal Flow Graphs During Systolic Array Processors Design

The algorithm for the transformation of Dependence Graphs, DGs, into Signal Flow Graphs, SFGs, during the design of Systolic Array Processors, SAPs, is presented. The transformation is a complex process, employing task scheduling, projection and the formation of recursive surfaces, i.e., hyperplanes corresponding to simultaneously executed processes during a common clock phase. A matrix method is developed, in order to overcome the limitation of more than 3-Dimensional euclidean space graphical modeling, used up to now, and based on the designer imagination. The proposed method is intended to be used, in the near future, by Design Automation CAD tools. Key–Words: Dependence Graph, modeling, Systolic Array Processors, task scheduling, recursive surfaces, projection vectors